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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTIAPPPULSE, CTI Application Pulse register</h1><p>The CTIAPPPULSE characteristics are:</p><h2>Purpose</h2>
        <p>Causes event pulses to be generated on ECT channels.</p>
      <h2>Configuration</h2><p>CTIAPPPULSE is in the Debug power domain.
    </p><h2>Attributes</h2>
        <p>CTIAPPPULSE is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE31</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">APPPULSE0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">APPPULSE&lt;x&gt;, bit [x], for x = 31 to 0</h4><div class="field"><p>Generate event pulse on ECT channel &lt;x&gt;.</p>
<p>Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the <a href="ext-ctidevid.html">CTIDEVID</a>.NUMCHAN field.</p>
<p>Writing to this bit has the following effect:</p><table class="valuetable"><tr><th>APPPULSE&lt;x&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No effect.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Channel &lt;x&gt; event pulse generated.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <ul>
          <li>
            The CTIAPPPULSE operation does not affect the state of the application trigger. If the channel is active, either because of an earlier event or from the application trigger, then the value written to CTIAPPPULSE might have no effect.
          </li>
          <li>
            Multiple pulse events that occur close together might be merged into a single pulse event.
          </li>
        </ul>
      </div>
    </div><h2>Accessing CTIAPPPULSE</h2>
        <p>It is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> whether a write to CTIAPPPULSE generates an event on a channel if CTICONTROL.GLBEN is 0.</p>
      <h4>CTIAPPPULSE can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0x01C</span></td><td>CTIAPPPULSE</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When SoftwareLockStatus(), accesses to this register are <span class="access_level">WI</span>.
          </li><li>When !SoftwareLockStatus(), accesses to this register are <span class="access_level">WO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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